To fabricate integrated circuits, multiple conductive layers are formed on semiconductor substrates to provide electrical contact between conductive components on the semiconductor devices. Since the dimensions of semiconductor devices have dropped below one micron design rules, the conductive layers are used to accommodate higher densities. The conductive layers are typically metal layers or metal features that are formed by chemical vapor deposition (“CVD”), physical vapor deposition (“PVD”), atomic layer deposition (“ALD”), or other electrodeposition techniques, such as electroplating or electroless deposition. To electroplate the metal feature, a seed layer is formed on a surface of the semiconductor substrate. The semiconductor substrate is directly attached to a positive electrode and a negative electrode. The surface of the semiconductor substrate is then plated with a desired metal by applying a voltage through the electrodes while an electrolyte solution containing the metal to be plated is flowed over the semiconductor substrate. The metal is electroplated onto the entire surface of the semiconductor substrate.
Electroplating is commonly used to form interconnect lines and vias in multilayer metal structures in a damascene process. Electroplating the interconnect lines and vias is one of many steps in fabricating the integrated circuits. In the damascene process, trenches are formed in the semiconductor substrate and are filled with a metal, such as copper, aluminum, or tungsten. After the metal is plated, the semiconductor substrate is polished, leaving the metal interconnect in the trench areas. One disadvantage with the damascene process is that since the entire surface of the semiconductor wafer is covered with the metal, undesired portions of the metal must be removed by polishing. A second disadvantage is that the metal is deposited nonuniformly on the semiconductor substrate because the electrodes are connected to edges of the semiconductor wafer, which causes a drop in potential towards the center of the semiconductor wafer.
Bipolar electrochemical processes have also been developed in which the desired metal is deposited on the semiconductor substrate without contact between the electrodes and the semiconductor substrate. For instance, U.S. Pat. No. 6,120,669 to Bradley discloses a bipolar electrochemical process that is used to toposelectively deposit a metal, such as a metal wire, between two metal particles. In addition, a method of plating metal interconnections on a semiconductor wafer using a bipolar electrode assembly is disclosed in U.S. Pat. No. 6,132,586 to Adams et al. A metallized surface of the semiconductor wafer is positioned opposite an anode and cathode of the bipolar electrode assembly. An electroplating solution of a metal to be plated is then flowed between the anode and a cathode and the metallized surface of the semiconductor wafer. A voltage is applied between the electrodes to plate the metal on the metallized surface of the semiconductor wafer. Relative motion is also provided between the bipolar electrode assembly and the semiconductor wafer while the voltage is applied. By moving the bipolar electrode assembly over the surface of the semiconductor wafer, electroplating of the metal is localized to a small area on the semiconductor wafer surface and provides more uniform deposits. The bipolar electrode assembly also enables one side of the semiconductor wafer to be simultaneously plated and deplated (electropolished). By applying a positive potential through the anode and a negative potential through the cathode, an area under the anode is electroplated while the area under the cathode is deplated.